High-Performance FPGA-Based Cryptographic and Image-Processing Co-Design for Real-Time Embedded Systems: Architectures, Trade-offs, and Implementation Strategies

Abstract

Background: Modern embedded systems for Internet-of-Things (IoT), autonomous sensing, and edge computing require tightly integrated solutions that deliver strong cryptographic protection and low-latency image/video processing on constrained hardware. Field-Programmable Gate Arrays (FPGAs) and System-on-Chip platforms combining ARM processors and programmable logic (SoC-FPGA) have emerged as the preferred substrates for these requirements due to their reconfigurability, parallelism, and energy-performance flexibility (Guerrieri et al., 2023; Tsai et al., 2023). However, co-designing high-throughput symmetric cryptography (notably AES) together with computationally heavy image/video processing and chaos-based primitives presents architectural, timing, and resource-allocation challenges that remain incompletely addressed in the literature (Li and Li, 2017; Visconti et al., 2020).

Objective: This article synthesizes the theoretical foundations and practical design strategies required to construct robust, low-latency FPGA-based systems capable of real-time AES encryption/decryption, chaos-based secure key generation, and accelerated image/video processing for embedded applications. It systematically surveys existing FPGA implementations, analyzes design trade-offs, and proposes a cohesive, extensible co-design methodology.

Methods: The study uses rigorous textual synthesis of peer-reviewed FPGA implementations, SoC integration examples, and high-level synthesis reports to derive an architecture-level methodology. The methodology covers modular AES pipelines, subpipelined and reconfigurable AES designs, chaos-based random/chaotic generators mapped to FPGA primitives, and image/video processing pipelines (including Harris corner detection and edge detection) implemented either with RTL or high-level synthesis. Performance and resource trade-offs are discussed through normalized metrics (throughput, latency, resource utilization, and energy considerations) derived from reported implementations (Li et al., 2017; Visconti et al., 2020; Rajasekar and Haridas, 2016).

Results: The synthesis identifies recurring design patterns that achieve throughput in the multi-Gigabit-per-second range for AES while maintaining low latency for video pipelines when carefully balancing pipeline depth, clock period, and resource duplication (Visconti et al., 2020; Li et al., 2023). Chaos-based generators provide compact entropy sources and can be integrated with lightweight ECC/TLS stacks for IoT coordinators (Elsayed et al., 2023; Bellemou et al., 2019). High-level synthesis offers rapid prototyping and maintainable code paths but sometimes trails hand-written RTL for area and peak throughput, necessitating selective RTL optimization in critical modules (Elsayed and Kayed, 2022; Sankar et al., 2023). Integration on Zynq-class SoC platforms enables flexible hardware/software partitioning for real-time fusion and control tasks (Yoon et al., 2016; Tsai et al., 2023).

Conclusions: A disciplined co-design strategy—combining reconfigurable subpipelined AES, chaos-based key generation, selective RTL optimizations, and HLS-accelerated image pipelines—yields systems capable of secure, real-time operation for many embedded applications. Future work should empirically validate energy models across device families and explore dynamic reconfiguration policies that trade security strength, throughput, and power in response to runtime requirements (Del-Valle-Soto et al., 2020; Visconti et al., 2020).